This invention relates to integrated circuits and, more particularly, to configurable register circuitry with error detection and error recovery capabilities in integrated circuits.
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which has led to performance increases. However, more recent technology nodes have seen a significant slow-down in the reduction of delays and thus to a slow-down in the performance increase.
Timing analysis is usually performed to determine the delay of paths between synchronous elements. The delay of the longest-delay path, which is sometimes also referred to as the critical path delay, determines the clock rate at which the synchronous elements in the integrated circuits are triggered. Timing analysis is required to account for the worst case scenarios and needs to take variability in combinational logic delays caused by manufacturing or environmental variations into account. In many cases, additional timing guard bands are required to ensure proper operation across manufacturing and environmental variations leading to overly pessimistic timing requirements and thus to slow clock rates.
Furthermore, some synchronous designs implemented in integrated circuits such as data paths in packet processing applications are tolerant of occasional timing faults caused by timing variability. Such timing variability tolerant designs are often able to handle the occasional timing fault, especially when the timing fault can be detected.